1. Field of the Invention
The present invention concerns a logic signals generating and sequencing circuit for charge transfer devices, notably charge-coupled devices.
2. Description of the Prior Art
In order to be driven, charge transfer devices need to receive a relatively large number of control logic signals with well-adapted temporal sequencing, as regards both the respective instants when the pulses, forming these logic signals, are produced and the respective phases of these pulses.
These control logic signals are used notably to achieve the transfer of charges within the matrix sensor (horizontal transfer, vertical transfer, transfer from the image plane to the memory plane etc.), the delivering of the output signal at a precise rate and as a function of an external synchronizing signal, zero-setting operations, etc. It is these signals that shall hereinafter be designated by the general term: "control logic signals".
The number and characteristics of these signals depend both on the class of sensor used (frame transfer sensor, row transfer sensor etc.) and, within one and the same class of sensor, on the driving mode used to transfer the charges. This driving mode may vary very greatly between one manufacturer and another and even, for one and the same manufacturer, between one reference of a circuit and another.
Until now, these control logic circuits were produced by a set of specialized circuits, the diagram of which is shown in a simplified way in FIG. 1.
A clock 1, generally a quartz crystal clock, produces a clock signal referenced CK, of the order of 8 to 15 MHz, applied to a synchronized signals generator 2 which also receives an external synchronization pulse SYN designed for the synchronization of successive frames, this signal SYN generally being a 50 or 60 Hz signal.
The output signal of the synchronized signals generator 2 is applied, in input, to a sequencing control circuit 3 which produces the different logic control signals .phi.l . . . .phi.N needed to drive the charge transfer device 4 through a driver stage 5 which provides for the matching of the voltage and current levels as a function of the needs of the charge transfer device.
For, the sequencing control generally produces TTL type signals, namely signals for which the two logic levels correspond to 0 and 5 volts. These voltages are not those needed by the sensor to work. Furthermore, the current drawn by the sensor is generally far greater than the possibilities of the sequencing logic circuit which is usually a MOS technology circuit.
Moreover, as charge transfer devices generally have a number of defective pixels, the defects are corrected so as to make them invisible (for example by reproducing, for the defective pixel, the voltage level corresponding to the illumination of the immediately preceding pixel).
This correction is made, upon command from the sequencing circuit 3, by the circuit 6 which processes the video signal given at the output of the sensor 4. To this effect, the positions of the defective pixels have been previously stored in an external memory 7, generally a PROM delivered at the same time as the sensor, the defects of which it memorizes.
The sequencing control circuit 3 is connected to the PROM 7 by an address bus and a data bus and, at each row, it interrogates the PROM to find out whether there is a defect on this row and, if so, to ascertain the horizontal position of this defective pixel. It will then, at the requisite instant, deliver the signal COR to the video processing circuit 6 (it will be noted, in this respect, that it is possible in this way to memorize only one defective pixel per row; this is generally enough, but necessitates the removal, in a preliminary sorting-out operation, of those sensors that do not meet this condition).
These prior art circuits have a number of drawbacks.
First of all, as will be easily understood, the sequencing control circuit is a circuit specific to a particular sensor (for example, a sensor of the Sony ICX021L type, the corresponding sequencing control circuit will be the CX23047A, associated with a synchronized signals generator CX7930 and a PROM MB6052).
It is thus seen that, since these are dedicated components, as many different types of synchronizing and rate-setting cards are required as there will be different types of sensors used.
Furthermore, at the level of the sensor, these cards are relatively bulky inasmuch as it is necessary to provide for several different discrete circuits (circuits 2, 3 and 7) with their respective interconnections.
Moreover, it would not be possible to combine the circuits 2, 3 and 7 in a single integrated component because the memory 7 contains a specific programming associated with a given copy of a sensor, and it is always necessary for the PROM to remain separate from the rest of the circuit, so that it can be exchanged if, for example, the sensor is exchanged.